1. Field of the Invention
The embodiments of the invention generally relate to field effect transistors and, more particularly, to fin-type field effect transistors having different channel region heights and, thus, different effective channel widths.
2. Description of the Related Art
As transistor design is improved and evolves, the number of different types of transistors continues to increase. Multi-gate non-planar metal oxide semiconductor field effect transistors (FETs), including dual-gate non-planar FETs (e.g., finFETs) and tri-gate non-planar FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects over planar FETs.
Dual-gate non-planar FETs are FETs in which a channel region is formed in the center of a thin semiconductor fin. The source and drain regions are formed in the opposing ends of the fin on either side of the channel region. Gates are formed on each side of the thin semiconductor fin, and in some cases, on the top or bottom of the fin as well, in an area corresponding to the channel region. FinFETs are a type of dual-gate non-planar FETs in which the fin is so thin as to be fully depleted. The effective fin width is determined by the fin height (e.g., wide fins can cause partial depletion of a channel). For a finFET, a fin thickness of approximately two-third the length of the gate (or less) can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al., which is incorporated herein by reference
Tri-gate non-planar FETs have a similar structure to that of dual-gate non-planar FETs; however, the fin width and height are approximately the same so that gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. The height to width ratio is generally in the range of 3:2 to 2:3 so that the channel will remain fully depleted and the three-dimensional field effects of a tri-gate FET will give greater drive current and improved short-channel characteristics over a planar transistor. For a detail discussion of the structural differences between dual-gate and tri-gate FETs see “Dual-gate (finFET) and Tri-Gate MOSFETs: Simulation and Design” by A Breed and K. P. Roenker, Semiconductor Device Research Symposium, 2003, pages 150-151, December 2003 (incorporated herein by reference).
Recently, static random access memory (SRAM) cells (e.g., 6T-SRAM cells having two pass-gate transistors, two pull-up transistors and two pull-down transistors) have incorporated such multi-gate non-planar FETs. SRAM cells are typically designed with stronger pull-down strength, where the width ratio of pull-down (drive) FETs to pass-gate (load) FETs (i.e., the beta ratio) is greater than approximately two. One method of achieving such a beta ratio (i.e. a greater effective channel width in the pull-down transistors as compared to the pass-gate transistors) in an SRAM cell is by incorporating multiple fins into the pull-down FETs and/or pass-gate FETs (e.g., to achieve a ratio of 2:1). However, due to the conventional lithographic techniques used to pattern semiconductor fins, it may be difficult to fit the multiple fins required within the allotted space. Additionally, frequency doubling of fin pitch is not easily achieved using current state of the art lithographic technology, and thus, multi-gate non-planar FET SRAM cells may be compromised for either density or performance.
Therefore, there is a need in the art for an improved semiconductor structure and an associated method of forming the structure that allows a greater effective channel width to be achieved in one multi-gate non-planar transistor as compared to another on the same wafer.